In many data communication architectures a clock signal is not transmitted with the data, requiring a receiver to have the ability to recover the clock signal from the transmitted data. For example, in FIG. 1, transmitting device 110 has a first clock reference 140 that it transmits data based on, while receiver 130, has a separate clock reference 150. Since no clock signal is transmitted over bus 120, receiver 130 must recover the clock signal from the transmitted data.
Prior art requires the use of data recovery circuits to recover the clock from serial data streams in devices called tracking receivers. Various tracking architectures have been used for this purpose. For example, many loop architectures including phase locked loop (PLL) based and delay locked loop (DLL) based architectures have been used. These circuits have various disadvantages. A PLL includes an oscillator that injects noise into the surrounding system. Furthermore, a PLL typically uses a voltage level to control its oscillation frequency, which is prone to frequency distortions introduced through low levels of noise on the control lines. A PLL also includes an analog loop filter to dampen input noise, which typically is an RC time constant network that consumes a relatively large amount of on-die area. DLL based architectures are also prone to frequency distortion and utilize analog filters which consume a relatively large on-die area. In addition, a DLL has a finite delay range.
Current clock recovery circuits have begun to use digital phase interpolation to overcome the aforementioned disadvantages. These digital phase interpolation circuits are known as phase interpolators. A specific implementation of a phase interpolator can be found in the patent application with Ser. No. 09/891,466, now U.S. Pat. No. 6,943,606. Typical phase interpolator loops determine if an actual sample of data is earlier or later than an ideal sampling point. From this determination, an out-of-phase detection signal, which can represent an advance or retard signal, is digitally filtered. To minimize unwanted phase adjustments due to noise injected on the incoming data stream, it is preferable to keep the digital filter fairly deep.
However, current phase interpolators cannot adequately filter larger PPM errors. When larger PPM errors are introduced the phase interpolator must step the clock used to sample the incoming signal much faster to make up for the larger PPM error. Unfortunately, when the rate of adjustment is increased the amount of digital filtering that may be done decreases. In some cases, where a relatively large PPM error, such as 5000 PPM, is introduced, there is almost no digital filtering. Without filtering, the result would be a receiver with an unacceptable high sensitivity to jitter on the incoming data stream, which would lead to incorrect phase adjustments and errors in the system.